Strain engineering is an important method to enhance the performance of advanced CMOS devices. Process-induced local strain, is currently the mainstream technology used to increase the hole mobility in advanced pMOS transistors. Here, recesses are etched in the source and drain regions and SiGe is selectively deposited in the recesses to introduce uniaxial compressive strain in the channel by using continuously increasing Ge concentration in the epi film.

Electron mobility improvements in nMOS transistors have, to date, been largely achieved through the use of stress liners, but this technology becomes less effective with continued scaling. As such, selective epitaxial growth of Si:C in the source/drain is being developed as a method for introducing compressive strain into the channel for potential adoption at the 22nm node and beyond. In recent years, various mobility-improvement technologies using process-induced local stresses, such as eSiGe source/drain (S/D), stress liner, gate stress and STI stress have been developed. Further eSiC is on the way.

For NMOS application, SiC can be used in the recessed areas to create tensile stress in the channel, since the lattice constant of SiC is smaller than that of silicon. The tensile stress is transferred into the channel and increases the electron mobility.

 eSiGe S/D recessed PMOS on (110) channel orientation with hole mobility booster observed.

 eSiC recessed NMOS with eletronic mobility booster observed.